WHEN:
Thursday, October 18, 2012 9:00 am
Pacific Time (GMT-08:00)
Thursday, October 18, 2012 12 noon
Eastern Time (GMT-05:00)
Thursday, October 18, 2012 5:00 pm
UK Time (GMT)
ChipStart has been pioneering the transitions to IP Subsystems for almost 3 years. SoC verification and software integration can be a difficult, iterative process. We invite you to attend our 1 hour webinar and hear how ChipStart customers are producing lower power, smaller designs using Non-Volatile Memory solutions from our premier partner, Novocell Semiconductor.
Novocell's patented and unchallenged Smartbit-based antifuse OTP macros have been silicon-proven at all major foundries worldwide and the IP is fully standard CMOS without need for any post process steps, special masks, or other steps or bakes. We provide antifuse one time programmable (OTP) nonvolatile memory (NVM) IP in sizes from 8bits to 4Mbits for use in replacing Foundry eFuse, for trimming, calibration, register uses, code storage, configuration, feature enablement, security/authentication, encryption key storage/embedding, device/serial number identification, etc. I am confident we can meet your OTP needs.
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While viewing this presentation, you will be able to submit questions to the presenters. They will respond either via email to all submitted questions, or if there is enough time during the Q&A session.
At ChipStart, it is our belief that in order for many companies to compete and thrive in their respective market segment, they must adopt or accelerate their IP outsourcing strategies. The new economics present a case study that quantifies the value of even small time to market windows, and how adopting IP outsourcing strategies actually lowers risks and improves productivities. This webinar highlights one such strategy – efficient FPGA-based SoC Prototyping.
We look forward to hosting you.
Best regards,
ChipStart
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