Memoir Systems Wins DesignVision Award at DesignCon 2012
Memoir’s Algorithmic Memory® Awarded Top Prize in Semiconductor & IP Category
SANTA CLARA, Calif.--Memoir Systems Inc., the Semiconductor Intellectual Property (SIP) provider that delivers breakthrough memory performance today announced that it won the DesignCon 2012 DesignVision Award for the Semiconductor & IP Category with its Algorithmic Memory. The award was presented at DesignCon 2012 held in Santa Clara, California January 30 - February 2, 2012. The DesignCon technical committee was comprised of 130 engineers and industry editors who evaluated products from hundreds of nominees to choose the winners. Winners were selected based on three criteria: how well the product met the market’s vision and offered unique insight into customer needs; the originality of the solution and if it offered a new approach to meeting the market needs; and the quality of the implementation and how will it fits market requirements.
Adam Kablanian, CEO of Memoir Systems noted, “We are very pleased and excited to have our Algorithmic Memory honored by such a well known and esteemed group as DesignCon. We just formally introduced our technology in October of 2011 so it is especially gratifying to see how quickly we are gaining recognition in the marketplace. We believe that this award also validates the strength and quality of our technology, and how well it addresses the specific design needs of embedded memory developers and system architects.”
Kablanian added, “Memoir’s Algorithmic Memory technology is the result of the creative efforts of the entire team at Memoir Systems. However, it would not be possible without the vision, commitment, and tireless pursuit of excellence of the two co-founders of the company, Sundar Iyer, CTO and Da Chuang, COO.”
About Memoir Systems Algorithmic Technology
Memoir Systems’ Algorithmic Memory technology is implemented as standard RTL built around existing embedded memory macros. It presents multiple memory interfaces that can all be accessed simultaneously, giving up to 10X more Memory Operations Per Second (MOPS). Memory performance can now be viewed as a configurable entity so that memory performance characteristics, such as the number of read, write interfaces and any special requirements regarding area and power can be specified. In addition, Memoir’s synthesis platform can automatically select suitable memory macros from a memory IP library, and incorporate memory algorithms to synthesize a new memory that is custom-made for the targeted application.