MEMGEN: Embedded SRAM Compiler

Today's SoC designers have to simultaneously optimize embedded memories for speed, power, performance and yield/cost.  By using ChipStart’s MEMGEN Embedded Memory Compiler, we now offer designers a user-friendly memory technology that excels in all three performance metrics at once.

MEMGEN Features

Some of MEMGENs features include:

  1. Flexible aspect ratios through column and I/O multiplexing
  2. Separate input and output buses
  3. Flow Through, Pipelined Read options
  4. Write-through mode
  5. Duty-free clock cycle
  6. Complete interface for EDA tools
  7. Allows routing over the array with higher metal layers
  8. Flexible redundancy support:
  • 1 or 2 dimensions
  • Laser or e-fuses

MEMGEN Configurability

MEMGEN is a configurable memory compiler. Some of the configuration options include:

1. BIST (Built-In Self Test) Aware

  • Customer may use internal test muxes or external BIST
2. Area or Performance Switch
  • Customer sets compiler priority switch to compile for optimal speed or size
3. Byte Masking
  • Subword select option
4. Port A/B setup mode (Read/Write) option (for DP SRAM)
5. Security and Test Mode for OTP NVM
6. Optional ECC
7. Selectable Charge Pump Option for OTP NVM Cell Programming
  • Built in internal VPPI source or External source
8. Single clock option (for DP SRAM)

GDS

MEMGEN Memory Topologies

  • Single-port Synchronous Static Random Access Memory (SP SRAM)
  • Dual-Port synchronous Static Random Access Memory  (DP SRAM)
  • Register File One-Time Programming Read Only Memory (RF OTP ROM)
  • One-Time Programming Synchronous  Read Only Memory (OPT ROM SYN)
  • One-Time Programming Asynchronous Read Only Memory (OPT ROM ASYN)
  • Flash Memory

Memory Compiler Type, Availability and Silicon Status

Compiler description

Memory Type

Process

Status

Single-ported Synchronous Static Random Access Memory

SP SRAM

0.25u

Tested in silicon

Dual-Ported synchronous Static Random Access Memory 

DP SRAM

0.25u

Tested in silicon

Register File One Time Programming Read Only Memory

RF OTP ROM

0.25u

Verified

One Time Programming Synchronous  Read Only Memory

 OTP ROM

0.25u

Verified

One Time Programming Asynchronous Read Only Memory

 OTP ROM

0.25u

Verified

Configurable One Time Programming Read Only Memory

 COTP ROM

0.13u

Tested in silicon

One Time Programming Asynchronous Read Only Memory

 OTP ROM

0.13u

Tested in silicon

One Time Programming Asynchronous Read Only Memory

 OTP ROM

0.13u

Tested in silicon

Single-ported Synchronous Static Random Access Memory

 SP SRAM

0.18u

Verified

Single-ported Synchronous Static Random Access Memory (Low Voltage)

 SP SRAM

0.18u

Verified

Single-ported  Dynamic Random Access Memory

  DRAM

0.25u

In development now

MEMGEN Output Views

MEMGEN produces several output view:

MEMGEN Front-End Views:

    • Data Sheet (*.ds)
      • Short specification with description of memory instance (size, PVT, timings, power consumption etc.)
    • Functional Model Verilog (*.v)
      • For behavioural model including timing information
    • Library Data Physical Information (*.lef)
      • Timing information *.lib (liberty file)
    • Cell Arrangement (*.txt)
      • Formatting information for pads setup

MEMGEN Back-End Views:

    • Layout Data GDSII (*.gds)
    • Circuit Netlist (*.net)
      • For electrical circuit for verification (legacy OrCAD format)
      • Also available in Cadence (*cdl) format

For more information please contact us