Wide-Band High-Frequency Digital PLL

In an effort to continually offer our customers the most advanced, highly differentiated solutions on the market, we are proud to introduce this revolutionary Wide-Band High-Frequency Digital PLL.

This Digital PLL is a totally-integrated (no off-chip components) Clock-Driver and Clock-Multiplying-Unit IP block with fractional-N division to allow for non-integer clock multiplication and spreading. This block is intended for applications such as the CMU in a SERDES block at data rates as high as 15 Gbs (and potentially higher), and for clock-driver applications where the frequencies are not integrally related.

This IP block is a digital phased-lock-loop, plus an integrated voltage and current reference, a variety of input amplifiers (single-ended and differential, dc and ac-coupled), a number of programmable dividers, a serial interface for programming, and a high-speed 50 ohm driver capable of driving off-chip at full-speed. The specification is for the High-Speed Digital PLL (HSDPLL) to operate between 0.5GHz and 7.5GHz over process corners and between -40 and 125 degrees celsius; the first measured sample (on TSMC CL040G process) locks for output frequencies between 0.144GHz and 10.8GHz, dissipates 32 mw (at a 5GHz output), and requires a 0.11 mm^2 area (not including pads and the output driver). Jitter measurements (after the output driver) indicate total rms accumulated jitter of 1.6ps at 5GHz output frequency.

What is a Digital PLL?

Practically all modern PLL’s are actually mixed-mode analog/digital blocks; what is commonly meant by a Digital PLL is a PLL that is mostly digital, that does not have an analog loop filter, and that also does not have analog charge-pump circuits. These sub-components are replaced with digital equivalents in a Digital PLL.

Why a Digital PLL?

  1. Wide Range and Programmability: A digital PLL is much easier to design to be used over a wide range of reference frequencies and output frequencies. The main reason for this is the dynamics of the integral signal path automatically track with the reference frequency. This should be compared with an analog approach where the analog loop filter must be ‘digitally trimmed’ for different bandwidths and reference frequencies, and the tuning range is limited. In addition, a highly-programmable digital approach can be digitally adjusted for many different application requirements; this allows for a One Size Fits All, minimizing both costs and support complexities. The programmability includes output impedance, loop bandwidth, output division ratio, VCO load capacitance, input reference amplifier type, etc.

  2. Predictability: the PLL is primarily composed of digital logic circuits which are highly predictable especially in sub-micron processes. What you simulate is what you get. Digital circuits are not affected (to the same degree) by analog issues such as leakage currents through loop capacitors, offset voltages due to transistor mismatches, substrate noise, reference feedthrough, etc (effects minimized, not eliminated). Predictability is critical as one goes to 40nm and smaller technologies; a second iteration caused by a poorly working PLL can incur millions of dollars of costs and loss of revenue and months lost in time to market.

  3. Porting: porting a PLL to a new technology is much faster and involves much less risk for a Digital PLL; for example, two silicon fabrication iterations, as required to center an LC oscillator, are not necessary. The GSC Digital PLL was designed using a technology independent approach, and practically all parameters (including loop transfer-function parameters) accurately scale proportional to the oscillation frequency. The bias circuits are all done in the high voltage option, and their absolute sizes accommodate all popular high-voltage options (1.8V/0.18um, 2.5V/0.25um, and 3.3V/0.35um), the minimum channel lengths accommodate higher voltages, while they can be used with a high-voltage as low as 1.62V and as high as 4V (a 5V high-voltage is also possible with minimal changes). Porting simply involves transferring the digital library (which again has been designed in a technology-independent manner) and modifying the resistors in the bias circuits for the new resistivity. Any process uncertainties are calibrated out at start-up, or adaptively digitally trimmed during circuit operation, without glitches. Another, strongly related characteristic is customization is much faster, cheaper, and safer, as it generally involves minimal logic changes only.

  4. Size: because the loop-filter and analog charge pumps have been eliminated, the size ( is similar to or smaller as compared to analog approaches; this is especially true as one goes to smaller technologies.

  5. Jitter: a major source of jitter for analog PLL’s (often the dominant source of jitter) comes from the loop filter, charge-pumps, and V/I conversion circuits. This is especially the case when non-calibrated charge-pump offsets, and power-supply noise are considered. These jitter noise sources can be significantly minimized with a properly designed digital approach. Currently, the accumulated rms jitter has been measured (using 1667 golden filter) at 1.6ps for a 5GHz output.

  6. Programmability: it is possible to design a Digital PLL to have a wide range of operation (without a performance penalty), and to be highly reconfigurable for many different frequencies and applications. A significant ramification of this is only a single PLL need be supported for many applications (and technologies).

Why Not?

Historically, the digital update, and the digital phase-detector have injected large jitter at each update; digital PLL’s have not obtained the jitter performance of analog PLL’s. GSC has solved the glitch problem at digital updates, has a significantly superior ring-oscillator, has greatly minimized charge-pump, loop-filter, and V/I conversion noise, etc. Its approach and its jitter performance, for a given power, oscillation and reference frequencies and loop bandwidth, is superior to other ring-oscillator-based approaches, and approaches the jitter performance of many LC-based approaches.

For more information, please contact us