Circuit Level Consulting
Smaller MOSFET widths and lengths and other layout-dependent issues in today’s CMOS processes (length of diffusions, well proximity effects, etc.) necessitate moving beyond simple Worst Case – Best Case analysis that has been done in older technologies to ensure functioning silicon with acceptable yields. Understanding at a quantitative level the limits of the SPICE models provided by the foundries, and how these models apply to the sub-circuits within memory, analog and IO IP is critical in 180nm CMOS process nodes and below.
In memories, bitcell yield is affected by both read stability and write-ability which both need to be evaluated using local and global mismatch effects. Similarly sense amplifier and complete datapath circuitry requires a thorough mismatch analysis before any level of confidence on the memory’s parametric robustness can be declared. If available early on, these results can be used in the overall system architecture phase when decisions are being made about how much ECC and/or redundant elements to use. In the analog domain, everything from opamp offset to bandgap start-up circuitry can be adversely affected by local mismatch that is larger than expected.
ChipStart Circuit Level Consulting performs such analysis on all its designs in order to provide the customer with as quantitative prediction as possible as to the overall parametric yield of the IP. We also perform design reviews containing similar analyses on our clients’ other IP when there are concerns about circuit manufacturability.