DDRx Controller and DDRx PHY

Chipstart offers a full range of DDR solutions (Integrated and non-integrated DDRx PHY and DDRx Controller) including the latest standards: DDR4, DDR3, DDR3/2, DDR2, LPDDR and mobileDDR. A fully integrated DDR2/3 controller and DDR2/3 PHY has been completely verified to provide support up to DDR3-2133. Support for various foundry and process nodes is provided with the solution, including TSMC 28nm HPM. In addition, a verification suite is included to reduce design cycle time. The Controller and PHY products are detailed below.

 

Memory Solution Overview

DDR Controller Core Products

The DDR Controller family supports a wide variety of DDR memories including:

  • DDR4NEW Starburst
  • DDR3
  • DDR3/2
  • DDR2
  • DDR
  • SDR
  • LPDDR3
  • LPDDR2
  • mobileDDR
  • mobileSDR

The DDRx SDRAM Controller Core is designed for use in applications requiring high memory throughput, high clock rates and full programmability. The core accepts commands using a simple local interface and translates them to the command sequences required by xDDR or DDRx SDRAM devices. The core also performs all initialization, refresh and power-down functions.

Highest Efficiency, Lowest Latency Achieved with QOS support - The core queues up multiple commands in the command queue and can reorder transactions to maximize efficiency. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput. QOS constraints have been added to further improve throughput and reduce blocking transactions. QOS features include multiple priorities among other parameters.

The core is provided with run-time programmable inputs for all memory timing parameters and configuration settings. This ensures compatibility with all DDR SDRAM configurations including DDR3. The core includes support of ODT, dynamic ODT, 2T timing and write leveling calibration.

A full set of Add-on Cores and an ASIC DDR PHY for use with the core including:

  • Bus Interface, AHB and AXI
  • Virtual FIFO, variable latency and bypass modes
  • Multi-Port Arbiter
  • Reordering
  • Read-Modify-Write
  • ECC
  • Multi-Burst
  • Memory Test
  • Data Analyzer
  • BIST

DDR3/2 PHY

  • Supports up to DDR3-2133 in wire bond packages
  • Narrow IO pad pitch for tighter integration
  • Small size
  • Low clock skews, easier to close timing

For more information, please contact us.