A growing set of IC applications require a high voltage interface. Examples include power management, power conversion and automotive chips with interfaces typically between 12V and 100V. Also mobile devices like cell phones and personal navigation devices today include interfaces above 10V to e.g. control and sense MEMS gyroscopic or compass sensors. And, most LCD/OLED display technologies require driving voltages between 10 and 40V. Besides the power, MEMS and display interfaces many devices include some sort of motor like the optical zoom lens and shutter control of digital cameras or the ‘silent mode’ vibrator in cell phones.
Though these applications represent fast growth markets, the underlying silicon process technologies lack standardized high performance ESD solutions. The purpose of ESD protection is to provide a safe, robust current path while limiting the voltage drop below the critical voltage determined by the circuit-to-be-protected. Today, different protection clamp types are used in the industry, each with significant performance and cost burdens that prevent generic use. The main problems with traditional solutions are high leakage current, large silicon area consumption and extensive custom (trial and error) development cycles for each process/fab change.
Further, to reduce the Bill of Materials (BOM) system makers are constantly shifting requirements that were once a system/PCB issue to the IC makers. IC makers designing high voltage applications need robust and reliable ESD technology that can meet a growing set of requirements.
Sofics has developed novel ESD devices that can solve the drawbacks of the current ESD concepts while strongly reducing the development and manufacturing cost. The Sofics ‘PowerQubic’ technology is currently used in the development of several products and is being evaluated for automotive (LIN) products. The 40V solution passed very severe automotive requirements like a 45V load dump (ISO 7637-2) and various transient latch-up conditions and high IEC 61000-4-2 stress pulses. Through the IP alliance partnership with TSMC these devices are now available in its 0.25um BCD technology with no strings attached (no NRE for standard cells, no royalty).
D. Christopher Keil, VP of Business Development, ChipStart LLC
The increasing momentum around adopting software-defined networking (SDN), which communications markets are currently experiencing, is accelerating the need for more comprehensive system management at the system-on-chip (SoC) level.
SDN introduces the notion of “random” events sequencing, such as changing the flow of a routing or switching path in real time from sources external to the network device. Random event change management, in turn, introduces new architectural challenges for communications SoCs because the state operation sequences to be executed are not predictable, as is the case when fully contained within the network device.
Traditionally, changing routing or switching flows are managed completely within the “closed” network system. The silicon that supports these devices then relies architecturally on making changes using uniform, well-coordinated and predictable system sequences. The entire change is managed within the confines of the switch or router. Predictability helps streamline the way these changes are sequenced at the silicon level given that other flows are also managed through the fabric.
Maintaining system integrity as a whole and maximizing system performance (making sure there are no excess cycles to perform these changes) is just a matter of optimizing the base architecture. Packet headers, packet inspection and table management schemes all are finely tuned today based on uniformity and predictability.
But the introduction of random change requests now means support silicon must operate with less predictability. Previously finely tuned switching fabric architectures will need significant redesign, including how the sequence of tasks through IP blocks are performed (order and structure), how data paths behave given a mix of requests, and how arbitration logic prioritizes all this for resource access.
This realization accelerates the need for more robust system management at the SoC level since the impact of SDN is architectural. The notion that this kind of state management can be handled during device development itself will only further lower overall schema reuse and also complicate maintaining compatibility of solution schemes from chip to chip.
SDN implies then not only a revisit of the core communications architectures, but also the need to add significant global system management into the silicon-based architecture so non-uniform and unpredictable change requests can be sequenced. Only then will system integrity and performance be maintained once again for random event management.