On 5th of March, 2013 at 9pm in Hannover, this year’s CeBIT trade fair has been opened. The ceremony was led by German Chancellor Angela Merkel and Polish Prime Minister Donald Tusk. One of the first devices which they got acquainted with during the ceremony, was the DQ80251 processor designed by Digital Core Design.
Hannover, March 5th, 2013. - Poland is this year’s Partner Country at CeBIT, world's largest IT trade fair in Hannover. It is no wonder, that the opening ceremony was honored by Chancellor Angela Merkel and Prime Minister Donald Tusk, who then together got familiar with the achievements of Polish IT.
One of the first booths they visited, was the one of Digital Core Design, a company from Bytom, which had designed the world's fastest 8051 processor – The DQ80251 is a sum of the experience gained during 14 years of existence – explained to the Chancellor and Prime Minister Mr. Jacek Hanke, DCD’s CEO - I can also assure you, that this is not our last word... The architecture developed by Polish engineers is over 66 times more efficient than the standard designed by Intel, thus the DQ80251 can execute one instruction in less than 3 nanoseconds. What does this mean in practice? - our CPU runs more operations in shorter time, while consuming less energy - and this is what the modern electronics is all about - Hanke adds. Among devices that were also presented to German Chancellor Angela Markel and Polish Prime Minister Donald Tusk during the opening ceremony, were the infrared detector designed in Poland (which was implemented in the Curiosity spacecraft, used in the mission to Mars) and the electronic dice - Dice +. For more information please visit www.cebit.de
Digital Signal Processing is taking on a new look. Our DSP partner, FireFlyDSP (www.fireflydsp.com), has now joined the Embedded Vision Alliance. With the ongoing evolution of computer vision technologies, many of these algorithms are migrating into the field of embedded vision and demanding chips with higher performance at lower power and cost. With applications like gesture recognition (in devices such as Microsoft's XBOX Kinect), lane detection and object recognition (in a variety of new vehicles), and face detection (for phones and social media), there are increasing opportunities for new SoCs.
The team at FireFlyDSP has leveraged their own backgrounds in image processing and algorithm optimization to develop an industry-leading technology for these growing applications. By working with the Embedded Vision Alliance, FireFlyDSP will bringing bring their insights and innovations to new, vision-related SoC developers.
For information on the FireFly DSP products, including the new FireFly64 DSP, contact Chip-Start or email info@fireflydsp.com
The rise of software defined networking introduces new ways to control and operate networks. Software programs can now personalize the behavior of the network by reprograming the switching fabrics with specific rules they would like to use. As a result from a silicon perspective, the biggest change in network operation then is the emergence of large volumes of control plane rule changes that have the effect of appearing “random” compared to the predictable flows traditionally controlled by the network. These changes are random because computer programs initiate them, not the network itself and so they are unpredictable in their timing or requirements.
Traditional fabrics have been built using structures optimized for match and forward tasks, and using deep packet inspection and packet classification techniques to learn about where the packets need to be forwarded in the network. These arrays are long in order to achieve line rate for multiple channels. To maximize performance, these arrays require packets to be inserted in the front of the pipeline, with classified packets coming out the end of the pipeline. Over time these traditional architectures have evolved such that specific and often specialized compute and state management is employed.
Introducing the random changes via SDN means the rules changes must occur during a pipeline stage, and as their volumes grow, in turn causes traditional architectures to operate far less efficiently. Eventually both reliability and scalability are compromised. What is emerging is an opportunity for network fabric developers to now leverage embed and general purpose microprocessor architectures as fabrics. These architectures are more optimized for random processing and in general will become adequately efficient as SDN grows. When coupled with companion chip sets that provide traditional IP packet processing tasks, such as TCP offload, these architectures become more efficient traditional network fabrics.
One of the design challenges when using embed or general purpose microprocessors is the continued need to employ data and control planes. SoCs that utilize these technologies and corresponding interconnects to connect multiple cores, have been heavily optimized for data plane operations. However, in networking, control plane is equally important.
SSM is the industry’s first merchant silicon optimized for control plane management using a SoC development methodology.
SSM compliments SoC data plane architectures while filling the void for control plane state management. SSM utilizes a software based policy driven state management approach, which enables SoCs to sufficiently mimic full control and data plane networking. The introduction then of SSM into a SoC enables full utilization of SoC methodologies for network fabric development.
By utilizing software policies that describe the nature of the SDN network personalization required, SSM can orchestrate the operation of the relevant subsystems on the SoC to create the behavior desired. If these subsystems are implemented using deeply embedded processing or re-programmable logic, specific actions that enforce SDN requests can be accommodated in real time while SSM manages the global state operations. As a result, predictability is restored to the network operations.
The SoC based fabric also becomes extremely flexible to adapt to increasingly diverse random requests. Thus, adaptive fabric operation is achievable by using the SSM subsystem to collect data about how the SoC is utilized. A second core processor can then use this data to monitor fabric use and determine optimal behavior patterns. This processor than chooses the SSM policies that reflect the optimizations. A library of SSM policies maintained in memory acts as real time middleware options that enable the fabric to constantly recalibrate and maintain optimal behavior.
The introduction of SDN causes traditional network fabric architectures to loose predictability and efficiency. Embedded and general purpose processors are more optimized for the random actions caused by SDN but lack specific network tasks and do not conventionally support robust control plane operations. SSM provides a complimentary control plane architecture which offers predictability and efficiency adequate for adopting SoC methodology for network fabrics. Additionally, SSM ushers in an adaptive behavior characteristic that enables SoC based fabrics to maintain optimal efficiency as the diversity of SDN random requests grows over time.
A growing set of IC applications require a high voltage interface. Examples include power management, power conversion and automotive chips with interfaces typically between 12V and 100V. Also mobile devices like cell phones and personal navigation devices today include interfaces above 10V to e.g. control and sense MEMS gyroscopic or compass sensors. And, most LCD/OLED display technologies require driving voltages between 10 and 40V. Besides the power, MEMS and display interfaces many devices include some sort of motor like the optical zoom lens and shutter control of digital cameras or the ‘silent mode’ vibrator in cell phones.
Though these applications represent fast growth markets, the underlying silicon process technologies lack standardized high performance ESD solutions. The purpose of ESD protection is to provide a safe, robust current path while limiting the voltage drop below the critical voltage determined by the circuit-to-be-protected. Today, different protection clamp types are used in the industry, each with significant performance and cost burdens that prevent generic use. The main problems with traditional solutions are high leakage current, large silicon area consumption and extensive custom (trial and error) development cycles for each process/fab change.
Further, to reduce the Bill of Materials (BOM) system makers are constantly shifting requirements that were once a system/PCB issue to the IC makers. IC makers designing high voltage applications need robust and reliable ESD technology that can meet a growing set of requirements.
Sofics has developed novel ESD devices that can solve the drawbacks of the current ESD concepts while strongly reducing the development and manufacturing cost. The Sofics ‘PowerQubic’ technology is currently used in the development of several products and is being evaluated for automotive (LIN) products. The 40V solution passed very severe automotive requirements like a 45V load dump (ISO 7637-2) and various transient latch-up conditions and high IEC 61000-4-2 stress pulses. Through the IP alliance partnership with TSMC these devices are now available in its 0.25um BCD technology with no strings attached (no NRE for standard cells, no royalty).
D. Christopher Keil, VP of Business Development, ChipStart LLC
The increasing momentum around adopting software-defined networking (SDN), which communications markets are currently experiencing, is accelerating the need for more comprehensive system management at the system-on-chip (SoC) level.
SDN introduces the notion of “random” events sequencing, such as changing the flow of a routing or switching path in real time from sources external to the network device. Random event change management, in turn, introduces new architectural challenges for communications SoCs because the state operation sequences to be executed are not predictable, as is the case when fully contained within the network device.
Traditionally, changing routing or switching flows are managed completely within the “closed” network system. The silicon that supports these devices then relies architecturally on making changes using uniform, well-coordinated and predictable system sequences. The entire change is managed within the confines of the switch or router. Predictability helps streamline the way these changes are sequenced at the silicon level given that other flows are also managed through the fabric.
Maintaining system integrity as a whole and maximizing system performance (making sure there are no excess cycles to perform these changes) is just a matter of optimizing the base architecture. Packet headers, packet inspection and table management schemes all are finely tuned today based on uniformity and predictability.
But the introduction of random change requests now means support silicon must operate with less predictability. Previously finely tuned switching fabric architectures will need significant redesign, including how the sequence of tasks through IP blocks are performed (order and structure), how data paths behave given a mix of requests, and how arbitration logic prioritizes all this for resource access.
This realization accelerates the need for more robust system management at the SoC level since the impact of SDN is architectural. The notion that this kind of state management can be handled during device development itself will only further lower overall schema reuse and also complicate maintaining compatibility of solution schemes from chip to chip.
SDN implies then not only a revisit of the core communications architectures, but also the need to add significant global system management into the silicon-based architecture so non-uniform and unpredictable change requests can be sequenced. Only then will system integrity and performance be maintained once again for random event management.