The shift in emphasis from performance to power constraints and cost reduction presents challenges for designers of today's multi-core and system-on-chip (SoC) ICs for mobile applications. Prominent examples are to be found in the cost- and power-sensitive SMART/SIM card and wearables markets. With the emergence of wearable electronics a new generation of gadgets is expected to drive brisk growth in the demand for electrical and electronic components, with the market value of components amounting to roughly 2/3 of the cost production. The wearable technology market revenue was $4.3 billion as of 2012 and is expected to reach to $14.0 billion by 2018, growing at an estimated CAGR of 18.93 % from 2013 to 2018. Components account for the largest percentage share of the overall revenue of global wearable technology, with a 66.2% share ($1.83 billion) in 2012 expected to grow to 73.0% of the total market by 2018.
Wearable applications call for components that integrate high functionality and computing power while maintaining good power efficiency. A typical consumer wearable device as shown in Figure 2 contains various sensors (e.g., for acceleration, temperature, IR and ambient light, pressure) an energy-efficient microprocessor, memory, wired and wireless communication, and power management. Limitations on the size of a wearable device drives integration of all possible functions into one SoC, and VivEng offers IP that can help SoC developers get to market quickly with highly competitive performance parameters.
Achieving the low power consumption demanded by wearable systems is a goal that requires designers to consider the full system architecture including hardware/software partitioning and power management strategies. Power management strategies often include clock scaling and gating, with independent control of multiple power domains. Many multi-core designs and SoC applications employ several low-dropout (LDO) regulators in their overall power management subsystem, to provide a voltage source for each power domain.
The primary task for an LDO regulator is to provide a stable output voltage even though the voltage of the external power supply (e.g., battery) changes over time or in response to variations in load current. LDO regulators can be used as standalone components or be embedded in an SoC design. A typical LDO regulator requires an external capacitor to improve the transient response, power supply noise rejection and stability. VivEng offers a family of LDO regulators that do not require an external capacitor, providing the advantages of lower pin counts, smaller packages, and reduced PCB area and BOM cost.
SMART CARD SoC
Figure 1 shows an example of a smart card SoC implemented using analog IP from VivEng. The design is partitioned into two main power domains, one for flash memory and another for digital circuitry including CPU and control logic. The power domains each have a dedicated LDO regulator, with one providing 1.8 V for flash memory and the other providing 1.2 V for the digital circuitry.
The first LDO regulator generates a 1.8 V supply voltage from an unregulated 1.62 V to 5.5 V supply, delivering a maximum load current (ILmax) of 20 mA. The LDO is always enabled and provides output even when the input voltage is insufficient for regulation (i.e., in saturation mode.) Power-up sequencing as required by the flash macro is also provided. It does not require any off-chip decoupling capacitor for its operation.
The second LDO regulator generates a 1.2 V supply voltage from an unregulated 1.62 V to 5.5 V supply, and is enabled only after the 1.8 V supply has settled. It offers two selectable operating modes: light-load (Idd = 3 uA, ILmax = 100 uA) and full-load ( Idd = 20 uA, ILmax = 20 mA.)
The design contains several other IP blocks from VivEng in addition to the LDO regulators: a trimmable oscillator that generates a master clock, an intrinsic thermal sensor that monitors die temperature, a photodetector that monitors ambient light intensity, and a thermal random bit generator that generates a stream of random bits.
The ambient light detector raises a signal a flag which can be used (for example) to initiate erasure and shutdown in the event the package is opened and the IC is exposed to light.
The 15 MHz oscillator generates a clock and does not require any external components. The IP features low power consumption, low temperature coefficient for the clock frequency, 50% duty cycle, instant start, and “on-the-fly” frequency adjustment with a 4-bit control bus.
The temperature alarm IP is essentially tied to the voltage reference block. It continuously monitors die temperature and asserts its output signal when the die temperature exceeds low or high temperature limits.
The thermal random bit generator generates a stream of random data bits based on a non-deterministic physical noise source. The IP has low current consumption and operates at a bit rate from 0.1 to 1 Mbps.
The IP blocks from VivEng use reference voltages and bias currents supplied by an IP block available from the same library. The reference voltage and current block is a high precision bandgap voltage and current reference circuit capable of working over a wide range of supply voltages. The block also generates a power-on reset and brownout signal for Vdd. All of the IP blocks are developed for the TSMC 90 nm flash memory process.
VivEng offers a portfolio of IP blocks that can be used standalone in different types of SoC or as a bundle suitable for SIM/SMART card or wearable SoC designs. The IP blocks are all self-contained and do not require any external components. The IP is fully characterized for the TSMC 90 nm flash process and the transfer to a 65 nm process is in progress.
- LDO – wide input power supply range, from 1.62 V to 5.5 V
- Low idle and operating currents for low power consumption
- Clock oscillator with adjustable frequency
- Thermal alarm for detecting over/under temperature conditions
- Ambient light alert with trimmable threshold
- High-speed random bit generation up to 1 Mbps
- Bandgap voltage and current reference